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ECL GATE CIRCUIT

机译:ECL门电路

摘要

PURPOSE:To simplify a circuit constitution, to reduce a power consumption, and to increase an emitter current in a low level. CONSTITUTION:When the base input of an emitter follower transistor Q3 is in the low level, the transistor Q1 of a differential gate is turned on, and the transistor Q2 of the differential gate is turned off. At that time, when the base input of the transistor Q1 is defined as V1E, the potential of a common emitter contact CE is defined as (V1E-VF). Therefore, the emitter voltage of a transistor Q4 is defined as (V1E-2VF), and then currents I4 passing through the transistor Q4 are defined as (V1E-2V1)/REF. On the other hand, when the transistor Q1 of the differential gate is turned off, and the transistor Q2 of the differential gate is turned on, the input of the emitter follower transistor Q3 is turned in a high level, and the potential VCE of the common emitter contact CE is defined as (VR-VF) for the transistor Q2 is turned on. Therefore, the currents I4 passing through the transistor Q4 are defined as (VR-2VF)/REF.
机译:目的:简化电路结构,降低功耗,并以低电平增加发射极电流。组成:当发射极跟随器晶体管Q3的基极输入处于低电平时,差分栅极的晶体管Q1导通,而差分栅极的晶体管Q2截止。此时,当将晶体管Q1的基极输入定义为V1E时,将公共发射极触点CE的电势定义为(V1E-VF)。因此,将晶体管Q4的发射极电压定义为(V1E-2VF),然后将流过晶体管Q4的电流I4定义为(V1E-2V1)/ REF。另一方面,当差动栅极的晶体管Q1截止,并且差动栅极的晶体管Q2导通时,发射极跟随器晶体管Q3的输入变为高电平,并且该晶体管的电势VCE变为0。晶体管Q2导通时,公共发射极触点CE定义为(VR-VF)。因此,将流过晶体管Q4的电流I4定义为(VR-2VF)/ REF。

著录项

  • 公开/公告号JPH04246912A

    专利类型

  • 公开/公告日1992-09-02

    原文格式PDF

  • 申请/专利权人 NEC CORP;

    申请/专利号JP19910011741

  • 发明设计人 YAMADA KAZUMI;

    申请日1991-02-01

  • 分类号H03K19/086;

  • 国家 JP

  • 入库时间 2022-08-22 05:42:41

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