synplify

synplify是synopsys的综合工具，但一般的硬件设计我们还不需要它，altera/xilinx都有各自的开发环境，但是当使用到soc设计时，一般使用的都是system verilog，而我们知道altera的开发环境实在太烂了，在system verilog上的支持远不如xilinx，这个时候只能想办法借助第三方工具了，当然我想synplify在FPGA上用的还是少，主要面向需要晶圆代工厂Foundry公司，做asic/soc设计上。由于synplify对文件添加的顺序性要求，顶层文件需要最后添加，综合顺序只能呆板的按照文件添加的顺序执行，一旦顺序不对就会报找不到包，对比下来还是xilinx更智能，不用综合选定top后就可以生成hierarchy结构，据说synplify的使用部分是因为synopsys的ip核被绑定只能使用synplify。
如何配合使用第三方综合工具和 Vivado IP (中文配音)

细数Quartus系列综合器对SystemVerilog支持上的5个槽点

参考

synplify.tcl

#-- Synplicity, Inc.
#-- Version Synplify Pro 8.8
 
#create a new project
project -new top.prj         #工程名命名为top
 
#add_file options
add_file -verilog "filelist.v"
add_file -fpga_constraint "top.fdc"
 
#implementation: "rev_1"
impl -add rev_1 -type fpga
 
#device options,本设计中使用的xilinx的K7系列
set_option -technology Kintex7
set_option -part XC7K410T
set_option -package FFG900
set_option -speed_grade -2L
set_option -part_companion ""
 
#compilation/mapping options
set_option -use_fsm_explorer 1
set_option -top_module "hello"  #顶层模块
 
#map options
set_option -frequency 50.000000  #外部晶振
set_option -auto_constrain_io 1
set_option -resolve_multiple_driver 1
set_option -srs_instrumentation 1
set_option -RWCheckOnRam 0
set_option -run_prop_extract 0
set_option -maxfan 10000
set_option -disable_io_insertion 0
set_option -pipe 1
set_option -update_models_cp 0
set_option -verification_mode 0
set_option -retiming 1
set_option -no_sequential_opt 0
set_option -fix_gated_and_generated_clocks 1
set_option -enable_prepacking 1
set_option -use_vivado 1         #指定布局布线的工具，本设计中指定vivado
 
# sequential_optimization_options
set_option -symbolic_fsm_compiler 1
 
# Compiler Options
set_option -compiler_compatible 0
set_option -resource_sharing 1
set_option -multi_file_compilation_unit 1
 
#automatic place and route (vendor) options
set_option -write_apr_constraint 1
 
#implementation attributes
set_option -vlog_std v2001
set_option -num_critical_paths 10
set_option -num_startend_points 10
set_option -project_relative_includes 1
set_option -hdl_define -set FPGA
 
set_option -include_path "./hdl/"    #设置源码路径
 
#simulation options
set_option -write_verilog 1
set_option -write_vhdl 0
 
#VIF options
set_option -write_vif 0
 
#set result format/file last
project -result_file "top.edf"
project -log_file "top.log"
 
#save run and close project
project -save top.prj
project -run
project -close top.prj

Makefile

SYNPLIFY_DIR = synplify
SYNPLIFY_TCL_FILE = synplify.tcl
SYNPLIFY_FDC_FILE = top.fdc
SYNPLIFY_VERILOG_FILE = filelist.v
SYNPLIFY_EDF_FILE = top.edf      #综合后的网表文件edf格式
SYNPLIFY_LOG_FILE = top.log
SYNPLIFY_VM_FILE = hello.vm      #综合后的网表文件vm格式，可作后仿真的输入
 
 
 
.PHONY:  run_synplify clean
 
run_synplify:
	echo "synthesize begin ..."
	rm -rf ${SYNPLIFY_DIR}
	mkdir ${SYNPLIFY_DIR}
	cd ${SYNPLIFY_DIR} && synplify_pro -batch synplify.tcl
	cp ${SYNPLIFY_DIR}/rev_1/*.edf ./${SYNPLIFY_EDF_FILE}
	cp ${SYNPLIFY_DIR}/rev_1/*.vm ./${SYNPLIFY_VM_FILE}
	cp ${SYNPLIFY_DIR}/top.log ./${SYNPLIFY_LOG_FILE}
	echo "synthesize finished!"
 
 
clean:
	rm -rf ${SYNPLIFY_DIR}
	rm -rf ./${SYNPLIFY_EDF_FILE}
	rm -rf ./${SYNPLIFY_LOG_FILE}
	rm -rf ./${SYNPLIFY_VM_FILE}