存为top.v,moduletop;regclk_reg;reg[3:0]in1_reg,in2_reg;wire[3:0]sum;wirecarry;addr4a4(clk_reg,in1_reg,in2_reg,sum,carry);parameter100;initialbeginclk_reg=0;in1_regrepeat(16*100)beginin1_reg+1;in2_regin1_reg,in2_reg,sum,carry);in1_reg,in2_reg,sum,carry);endin1_reg,in2_reg,sum,carry);$finish(2);endalwaysbegin#50clk_reg=~clk_reg;end...